1. Field of Invention
The present invention pertains to the field of memories. More particularly, this invention relates to a multi-port memory that sequences port accesses.
2. Art Background
A typical memory such as a static random access memory (SRAM) includes an array of memory cells arranged into rows and columns. Such an array usually includes word lines coupled to rows of the memory cells and bit lines coupled to columns of the memory cells. The word lines are typically used to activate the rows of the memory cells and the bit lines are usually used to read and write the memory cells that are activated by the word lines.
Such a memory may be arranged as a single-port memory or a multi-port memory. A typical single-port memory provides physical connections for only a single set of address/data lines. A typical multi-port memory provides connections for multiple separate sets of address/data lines. A common example of multi-port memory is a dual-port memory. Typically, a dual-port memory has the advantage of providing read and/or write access to stored data from two independent ports having independent timing with respect to one another.
Unfortunately, multi-port memories usually suffer from a variety of drawbacks. For example, the array in a typical prior multi-port memory includes extra word lines and bits lines in comparison to arrays in typical single-port memories. In addition, the memory cells in typical prior multi-port memories includes extra transistors in comparison to the memory cells in single-port memories. Such extra signal lines and transistors usually increase the circuit area and thereby increase manufacturing costs and decrease storage density. Moreover, the extra transistors and signal lines usually increase the power consumption of prior multi-port memories in comparison to single-port memories. Furthermore, the extra signal lines usually increase capacitance and noise in prior multi-port memories.
A multi-port memory is disclosed that sequences port accesses to an array of memory cells. The sequencing of port accesses enables the array to be implemented without the additional signal lines and transistors usually found in prior multi-port memories. The multi-port memory includes a port control circuit that senses accesses from different ports and that sequences the accesses as appropriate. The multi-port memory also includes an input/output structure for holding data associated with the sequenced accesses.
Other features and advantages of the present invention will be apparent from the detailed description that follows.